A.C. Plasma display panels are known in the art and, in general, comprise a pair of transparent substrates respectively supporting column and row electrodes, each coated with a dielectric layer and disposed in parallel spaced relation to define a gap in which an ionizable gas is sealed. The substrates are arranged such that the electrodes are disposed in orthogonal relation to one another, thereby defining points of intersection which, in turn, define discharge cells at which selective discharges may be established to provide a desired storage or display function. Such panels are operated with AC voltages and provide a write voltage which exceeds the firing voltage of the ionizable gas at a point on the panel, as defined by selected column and row electrodes, thereby producing a discharge at a selected cell. The discharge at the selected cell is continuously "sustained" by applying an alternating sustain voltage (which, by itself is insufficient to initiate a discharge). This technique relies upon the wall charges that are generated on the dielectric layers of the substrates which, in conjunction with the sustain voltage, operate to maintain discharges.
Details of the structure and operation of such gas discharge panels or plasma displays are set forth in U.S. Pat. No. 3,559,190 issued Jan. 26, 1971 to Donald L. Bitzer, et al.
Various attempts have been made to reduce the costs of AC plasma panel structures. One of the more successful is described in U.S. Pat. No. 4,772,884, entitled "Independent Sustain and Address Plasma Display Panel", by Weber et al The Independent Sustain and Address (ISA) technology has been successfully developed into a practical technology for AC plasma displays. ISA displays have a number of advantages including half the number of required address drivers and a reduction in the address driver power dissipation which allows the practical implementation of advances such as chip-on-glass packaging.
The ISA technology is based on the principle that the addressing and sustain operations have separate electrodes in the panel devoted exclusively to each operation. A pixel is addressed in a multi step process initiated by the application of address pulses to selected address cells. Plasma then spreads out from the address cells to selectively erase targeted pixels.
The prior art ISA structure is shown in FIG. 1. FIG. 2 shows an expanded view of the area in circle 10 in FIG. 1. The expanded view in FIG. 2 shows a basic nine cell group that is the repetitive unit in the ISA geometry. Each of the nine cells is defined in accordance with the types of electrodes that intersect to define a cell. In plasma panels that existed prior to the ISA technology, all cells on the panel were electrically identical and, in fact, were all display pixels. However, in an ISA panel, only four of the nine cells of a cell group are display pixels, i.e., P1, P2, P3, and P4. Those pixel cells are located at the intersections of four sustain electrodes XSa, XSb, YSa, and YSb. Thus, each cell group has four corresponding pixel cell types. As will be understood hereafter, each corresponding cell type (e.g., P1, P2, etc.) in each cell group is subjected to sustain potentials during the operation of a panel, but its response to such potentials is controlled by potentials imposed on address lines that intersect each cell group.
In addition to the four pixel cell types, there are five other cells in a cell group. At the center of the cell group is an address cell A which occurs at the intersection of two address electrodes XA and YA. There are also four coupling cells: C1, C2, C3, and C4 which occur at the intersections of a sustain electrode and an address electrode. The coupling cells are divided into two categories depending upon their position relative to the address cell. The C1 and C4 cells are called vertical coupling cells and the C2 and C3 cells are called horizontal coupling cells. It should be understood, that the terms vertical and horizontal are used merely to designate orthogonal orientations of conductors and cells and for easy reference purposes. No particular global orientation is to be implied therefrom.
In one preferred embodiment, all horizontal electrodes of the ISA panel reside on one substrate of a panel and are referred to as the Y electrodes. All vertical electrodes reside on an opposite substrate and are termed X electrodes. As is well known, an ionizable gas is positioned between the substrates and provides for selected cell illumination. The X address electrodes comprise electrodes 12, 14, 16 and 18 whereas the Y electrodes comprise electrodes 20, 22, 24, and 26. Each X electrode can be selectively addressed by a column address driver circuit 28 and each Y address line can be addressed by a row address driver circuit 30.
X sustain signals are provided by two, phased, sustain generators 32 and 34, with each of the aforementioned sustain generators coupled to a connected pair of parallel sustain lines (e.g. 36, 38). Each pair of sustain lines, e.g. 36, 38, is shorted together by shorting bars at either end, thus forming a sustain electrode pair. Alternating sustain electrode pairs on a given substrate are bussed together by a sustain bus and are connected to one of the two sustain drivers. Row sustain drivers 40 and 42 are similarly connected to interspersed row sustain pairs.
In FIG. 3, waveforms are shown which describe a basic cycle for an ISA plasma panel as described in the aforementioned U.S. Pat. No. 4,772,884. In a preferred mode of operation, two rows of pixel cells are initially turned ON. Then, an erase cycle is performed to selectively turn OFF pixels which the image data indicate should be in the OFF state. The waveforms of FIG. 3 assume that a "write two rows" cycle has already occurred. The selective erase of certain desired ON pixels encompasses two steps. The first step causes a discharge to occur in selected address cells along a selected YA address electrode (see FIG. 2). This results in the migration of wall charges into vertical coupling cells C1 and C4.
Prior to a selective erase cycle occurring, a reset pulse is applied to address lines to reset the wall voltages in vertical coupling cells C1 and C4 and in address cell A. A simultaneous application of sustain voltages to XSa, XSb and YSa, YSb sustain lines with the reset pulses will cause small discharges to occur in the coupling cells which serve to adjust their wall voltages.
Subsequently, erase address pulses 50 and 52 are applied to the XA and YA address lines respectively. This commences Step 1 of the selective erase procedure and its effect is shown in FIG. 4. The erase address waveforms are polarized so that the XA and YA electrodes are the anode and cathode respectively. Since the XA electrode is the anode, the plasma discharge 54, which occurs at address cell A, spreads predominantly towards vertical coupling cells C1 and C4. The voltage across the gaps in each of coupling cells C1 and C4 is such that the spreading plasma deposits significant negative charge into these cells.
Step 2 (see FIG. 4) of the selective erase address performs two degrees of selection. It commences after the trailing edge of erase address pulses 50 and 52 and upon the rise of selection potentials on the sustain electrodes. During Step 2, the selected YS and XA electrodes are the anode and cathode respectively. This polarization enables the plasma 56 generated by the discharge of a coupling cell to spread horizontally away from the cell and into neighboring pixel cells. By raising only the Y sustain line associated with a selected vertical coupling cell, the unselected vertical coupling cell, defined by the non-raised Y sustain line, will not discharge. By raising the X sustain line associated with a pixel to be erased, erasure selection of a pixel is accomplished.
Since the ISA technology relies on the discharge of the address cell to accomplish any addressing, there is always a small amount of light emitted from the panel during any addressing. This light takes the form of a short pulse or pulses emitted from the address cells and pixels involved in the address operation. When a panel is addressed at a high frame rate, such as the commonly used 60 Hz rate, this address light appears to the eye as a slight background glow that makes the OFF pixels appear to glow. This has the effect of slightly reducing the contrast ratio of the panel in a dark room, however this slight background glow is usually not detected by an observer in typical office lighting.
While the addressing light is not a problem for operation at high frame rates such as 60 Hz, it can be an annoyance at low frame rates. For instance, if the display is addressed at a frame rate of only 10 Hz, the eye is able to see the scanning of the address operations because it is below the eye's flicker fusion frequency and the addressing appears as an annoying background glow flicker instead of the continuous glow of the 60 Hz case.
Operation of AC plasma displays at frame rates lower than 60 Hz is necessary whenever there is insufficient addressing time to address all of the pixels in the panel at the full frame rate. This is important for displays having a larger number of pixels. Thus, if the time to address a single horizontal address line is 40 us, then a 640.times.400 pixel display can be addressed in 400.times.40 us=16 ms, which corresponds to a frame rate of 1/.016=62.4 Hz. However, a 1280 by 1024 pixel display using the same horizontal line address rate can only be completely addressed in 1024.times.40 us=40.96 ms which corresponds to a frame rate of 24.4 Hz. The 640 by 400 panel will have no observable background glow flicker, but the 1280 by 1024 will have an easily observable background glow flicker because the 24.4 Hz frame rate is well below the flicker fusion frequency of most observers.
AC plasma displays with large number of pixels are emerging as an important technology. The inherent memory feature of the AC plasma technology gives it a significant advantage over other display technologies because the ON pixels do not flicker for any update rate. In addition the memory function keeps the duty cycle of the pixels at one no matter what the size of the panel or the frame rate. This unity duty cycle keeps the display brightness at a high level, independent of panel size.
A major hurdle in using the ISA technology approach for large plasma panels, is the elimination of the background glow flicker for displays updated at low frame rates.
Accordingly, it is an object of this invention to provide a method for preventing observable flicker in a display panel, wherein addressing results in emitted light.
It is another object of this invention to provide an ISA plasma panel with an improved method for preventing observable flicker.
It is yet another object of this invention to provide large ISA plasma panels which, using prior art techniques would exhibit flicker, with a system for preventing observable flicker without significant extension of address times.